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CD4046BMS
December 1992
CMOS Micropower Phase Locked Loop
Description
CD4046BMS CMOS Micropower Phase-Locked Loop (PLL) consists of a low power linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signalinput amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if necessary. The CD4046BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4W Frit Seal DIP H1F Ceramic Flatpack H6W VCO Section The VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 and R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO and resistor R2 enables the VCO to have a frequency offset if required. The high input impedance (1012) of the VCO simplifies the design of low pass filters by permitting the designer a wide choice of resistorto-capacitor ratios. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at terminal 10 (DEMODULATED OUTPUT). If this terminal is used, a load resistor (RS) of 10k or more should be connected from this terminal to VSS. If unused this terminal should be left open. The VCO can be connected either directly or through frequency dividers to the comparator input of the phase comparators. A full CMOS logic swing is available at the output of the VCO and allows direct coupling to CMOS frequency dividers such as the Intersil CD4024, CD4018, CD4020, CD4029, and CD4050. One or more CD4018 (Preset Table Divide-By-N Counter) or CD4029 (Presettable Up/Down Counter) or CD4029 (Presettable Divideby-N Counter) or CD4029 (Presettable Up/Down Counter), or CD4059A (Programmable Divide-by "N" Counter), together with the CD4046BMS (Phase-Locked Loop) can be used to build a micropower low-frequency synthesizer. A logic 0 on the INHIBIT input "enables" the VCO and the source follower, while a logic 1 "turns off" both to minimize stand-by power consumption.
Features
* Very Low Power Consumption: 70W (typ.) at VCO fo = 10kHz, VDD = 5V * Operating Frequency Range Up to 1.4 MHz (typ.) at VDD = 10V, RI = 5k * Low Frequency Drift: 0.04%/oC (typ.) at VDD = 10V * Choice of Two Phase Comparators: - Exclusive-OR Network (I) - Edge-Controlled Memory Network with Phase-Pulse Output for Lock Indication (II) * High VCO Linearity: <1% (typ.) at VDD = 10V * VCO Inhibit Control for ON-OFF Keying and Ultra-Low Standby Power Consumption * Source-Follower (Demod. Output) Output of VCO Control Input
* Zener Diode to Assist Supply Regulation * Standardize, Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* FM Demodulator and Modulator * Frequency Synthesis and Multiplication * Frequency Discriminator * Data Synchronization * Voltage-to-Frequency Conversion * Tone Decoding * FSK - Modems * Signal Conditioning
Pinout
CD4046BMS TOP VIEW
PHASE PULSES 1 PHASE COMP I OUT 2 COMPARATOR IN 3 VCO OUT 4 INHIBIT 5 CI(1) 6 C1 (2) 7 VSS 8 16 VDD 15 ZENER 14 SIGNAL IN 13 PHASE COMP II OUT 12 R2 TO VSS 11 R1 TO VSS 10 DEMODULATOR OUT 9 VCO IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3312
7-886
CD4046BMS
Phase Comparators
SIGNAL INPUT (TERM. 14)
The phase-comparator signal input (terminal 14) can be direct-coupled provided the signal swing is within CMOS logic levels (logic "0" 30% (VDD-VSS). logic "1" 70% (VDD - VSS)]. For smaller swings the signal must be capacitively coupled to the self-biasing amplifier at the signal input. Phase-comparator I is an exclusive -OR network; it operates analogously to an overdriven balanced mixer. To maximize the lock range, the signal and comparator-input frequencies must have a 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to VDD/2. The low-pass filter connected to the output of phase-comparator I supplies the averaged voltage to the VCO input, and causes the VCO to oscillate at the center frequency (fo). The frequency range of input signals on which the PLL will lock if it was initially out of lock is defined as the frequency capture range (2fc). The frequency range of input signals on which the loop will stay locked if it was initially in lock is defined as the frequency lock range (2fL). The capture range is the lock range. With phase-comparator I the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the low-pass-filter characteristics, and can be made as large as the lock range. Phase-comparator I enables a PLL system to remain in lock in spite of high amounts of noise in the input signal. One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO center-frequency. A second characteristic is that the phase angle between the signal and the comparator input varies between 0o and 180o, and is 90o at the center frequency. Figure 1 shows the typical, triangular, phase-to-output response characteristic of phase comparator I. Typical waveforms for a CMOS phase-locked-loop employing phase comparator I in locked condition of fo is shown in Figure 2.
AVERAGE OUTPUT VOLTAGE VDD
VCO OUTPUT (TERM 4) = COMPARATOR INPUT (TERM 3)
PHASE COMPARATOR I OUTPUT (TERM 2) VCO INPUT (TERM 9) = = LOW-PASS FILTER OUTPUT
VDD
VSS
FIGURE 2. TYPICAL WAVEFORMS FOR CMOS PHASELOCKED LOOP EMPLOYING PHASE COMPARATOR IN LOCKED CONDITION OF fo.
VDD/2
0
90o
180o
SIGNAL-TO-COMPARATOR INPUTS PHASE DIFFERENCE
FIGURE 1. PHASE-COMPARATOR I CHARACTERISTICS AT LOW-PASS FILTER OUTPUT
Phase comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a three-state output circuit comprising p- and n- type drivers having a common output node. When the p-MOS or n-MOS drivers are ON they pull the output up to VDD or down to VSS, respectively. This type of phase comparator acts only on the positive edges of the signal and comparator inputs. The duty cycles of the signal and comparator inputs are not important since positive transitions control the PLL system utilizing this type of comparator. If the signal-input frequency is higher than the comparator-input frequency, the p-type output driver is maintained ON most of the time, and both the n and p drivers OFF (3state) the remainder of the time. If the signal-input frequency is lower than the comparator-input frequency, the n-type output driver is maintained ON most of the time, and both the n and p drivers OFF (3 state) the remainder of the time. If the signal and comparator input frequencies are the same, but the signal input lags the comparator input in phase, the n-type output driver is maintained ON for a time corresponding to the phase differences. If the signal and comparator-input frequencies are the same, but the comparator input lags the signal in phase, the p-type output driver is maintained ON for a time corresponding to the phase difference. Subsequently, the capacitor voltage of the low-pass filter connected to this phase comparator is adjusted until the signal and comparator inputs are equal in both phase and frequency. At this stable point both p- and ntype output drivers remain OFF and thus the phase comparator output becomes an open circuit and holds the voltage on the capacitor of the low-pass filter constant. Moreover the signal at the "phase pulses" output is a high level which can be used for indicating a locked condition. Thus, for phase comparator II, no phase difference exists between signal and comparator input over the full VCO frequency range. Moreover, the power dissipation due to the low-pass filter is reduced when this type of phase comparator is used because both the p- and n-type output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range, independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to its lowest frequency for phase comparator II. Figure 15 shows typical waveforms for a CMOS PLL employing phase comparator II in a locked condition.
AVERAGE OUTPUT VOLTAGE (V)
7-887
Specifications CD4046BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) 3 State Leakage Current VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V 3 State Leakage Current IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -100 -1000 -100 1.5 4 100 1000 100 V V V V nA nA nA nA nA nA -55oC
o
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7
MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+25oC, +125oC, -55oC 14.95
VOH > VOL < VDD/2 VDD/2
7-888
Specifications CD4046BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) GROUP A SUBGROUPS 1 3 1 3 LIMITS TEMPERATURE +25oC -55oC +25oC -55oC MIN MAX 4 4 160 160 UNITS mA mA A A
PARAMETER Quiescent Leakage Phase Comparator (Bias Amp Leakage)
SYMBOL
CONDITIONS (NOTE 1)
BIAS LKG VDD = 20V, VIN = VDD or GND PIN 14 Open Pin 5 = VDD VDD = 20V, VIN = VDD or GND PIN 14 = VSS or VDD Pin 5 = VDD
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 +25 C
o
LIMITS MIN MAX 360 UNITS mV
PARAMETER AC Coupled Signal Input Voltage Sensitivity (Peak to Peak) NOTES:
SYMBOL VS
CONDITIONS (NOTE 1) VDD = 5V, Input Frequency = 100kHz Sine Wave
1. Go/No Go test with limits applied to inputs. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) SYMBOL VOL VOL VOH VOH IOL5 CONDITIONS VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55 Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2
oC
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 +7
MAX 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 -
UNITS mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V
+125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low Input Voltage High
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
IOH15
VDD =15V, VOUT = 13.5V
1, 2
VIL VIH
VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V
1, 2 1, 2
7-889
Specifications CD4046BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Quiescent Leakage Phase Comparator (Bias Amp Leakage) SYMBOL BIAS LKG VDD = 5 VIN = VDD or GND CONDITIONS Pin 14 Open Pin 5 = VDD Pin 14 = VSS or VDD Pin 5 = VDD NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE +25oC/-55oC +25oC/-55oC +25oC/-55oC +25oC/-55oC +25oC/-55oC +25oC/-55oC +25oC +25oC MIN MAX 0.2 20 1.0 40 1.5 80 660 1800 UNITS mA A mA A mA A mV mV
VDD = 10 Pin 14 Open VIN = Pin 5 = VDD VDD or Pin 14 = VSS or VDD GND Pin 5 = VDD VDD = 15 Pin 14 Open VIN = Pin 5 = VDD VDD or Pin 14 = VSS or VDD GND Pin 5 = VDD AC Coupled Signal Input Voltage Sensitivity (Peak to Peak) VS VDD = 10V, Input Frequency = 100kHz Sine Wave VDD = 15V, Input Frequency = 100kHz Sine Wave
NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND AC Coupled Signal Input Voltage Sensitivity VS VDD = 5V Input Frequency = 100kHz Sine Wave 1, 2, 3 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V
mV
NOTES: 1. All voltages referenced to device GND. 2. Go/No Go test with limits applied to inputs. 3. See Table 2 for +25oC limit. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
7-890
Specifications CD4046BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 METHOD 5005 PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND 3, 5, 8, 9, 14 8 8, 9 8 VDD 12, 16 3, 5, 9, 12, 14, 16 3, 5, 12, 16 3, 5, 9, 12, 14, 16 2 14 9V -0.5V 50kHz 25kHz
Static Burn-In 1 1, 2, 4, 6, 7, 10, 11, Note 1 13, 15 Static Burn-In 2 1, 2, 4, 6, 7, 10, 11, Note 1 13, 15 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1, 2, 4, 6, 7, 10, 11, 13, 15 1, 2, 4, 6, 7, 10, 11, 13, 15
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V
7-891
CD4046BMS Design Information
This information is a guide for approximating the values of external components for the CD4046BMS in a Phase-LockedLoop system. The selected external components must be within the following ranges: 5k R1, R2, RS 1M
CHARACTERISTICS VCO Frequency
C1 100pF at VDD 5V
PHASE COMPARATOR USED 1
C1 50pF at VDD 10V
DESIGN INFORMATION VCO Without Offset R2 = VCO With Offset
f f
O 2fL
MAX
f
f
MAX
f
O
MIN
2fL
f
MIN VDD/2 VDD VDD/2 VDD
VCO INPUT VOLTAGE
VCO INPUT VOLTAGE
2 For Number Signal Input 1 2 Frequency Lock Range, 2fL 1, 2 1, 2 Frequency Capture Range, 2fC 1
Same as for Number 1 VCO will adjust to center frequency, fo VCO will adjust to lowest operating frequency, fmin 2fL = full VCO frequency range 2fL = fmax - fmin
IN R3 OUT (1), (2) C2 2fC 1
I = R3C2
2fL
1
Loop Filter Component Selection
IN R3
OUT
R4 C2
For 2 fC, see Ref. (2)
2 Phase Angle Between Signal and Comparator 1
fC = fL 90o at center frequency (fo) approximating 0o and 180o at ends of lock range (2fL) Always 0o in lock Yes No High Low
2 Locks On Harmonic of Center Frequency 1 2 Signal Input Noise Rejection 1 2
For further information, see (1) F. Gardner, "Phase-Lock Techniques" John Wiley and Sons, New York 1966 (2) G. S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965
7-892
CD4046BMS Block Diagram
*
SIGNAL 14 IN 16 VDD
*ALL INPUTS ARE PROTECTED
COMPARATOR IN * 3 PHASE COMPARATOR I PHASE COMP. I OUT 2 PHASE COMP. II OUT PHASE COMPARATOR II 13 1 PHASE PULSES R3 VSS 6 C1 7 R1 VSS R2 VSS 12 11 SOURCE FOLLOWER DEMODULATOR OUT 10 RS VSS C2 VCO BY CMOS PROTECTION NETWORK VDD
/N
VCO OUT 4
*VCO IN
9
LOW PASS FILTER
*
5
INHIBIT
VSS
8
15 ZENER
VSS
FIGURE 3. CMOS PHASE-LOCKED LOOP BLOCK DIAGRAM
Typical Performance Characteristics
o RI = 10k AMBIENT TEMPERATURE (TA) = +25 C VCOIN = VDD/2, R2 = , INHIBIT = VSS
CENTER FREQUENCY (fO) (Hz)
106 105 104 103
SUPPLY VOLTAGE (VDD) = 15V RI = 1M 10V 5V 15V 10V 5V 15V 10-1 1 10 106 RI = 10k CENTER FREQUENCY (fO) (Hz) 105 RI = 100k 104 RI = 1M 103 102
SUPPLY VOLTAGE (VDD) = 10V VCOIN = VDD/2, R = , INHIBIT = VSS AMBIENT TEMPERATURE (TA) = -55oC -55oC +125oC -55oC +125oC -55oC +125oC
10
2
RI = 100k
5V
10 10V 1 10-5 10-4 10-3 10-2
VCO TIMING CAPACITOR (CI) (F) TYPICAL CENTER FREQUENCY UNIT-TO-UNIT VARIATION VDD (V) 5 10 15 f/fO (%) 50 30 35
10 1 10-5 10-4 10-3 10-2 10-1 1 VCO TIMING CAPACITOR (CI) (F) 10
FIGURE 4. TYPICAL CENTER FREQUENCY AS A FUNCTION OF C1 AND R1 AT VDD = 5V, 10V, AND 15V
FIGURE 5. CENTER FREQUENCY AS A FUNCTION OF C1 AND R1 FOR AMBIENT TEMPERATURE OF -55oC to +125oC
7-893
CD4046BMS Typical Performance Characteristics
(Continued)
R2 = 10k AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VSS INHIBIT = VSS FREQUENCY OFFSET (fMIN) (Hz) 106 105 104 103 102 10 1 10-5 10-4 10-3 10-2 10-1 1 R2 = 1M R2 = 100k
SUPPLY VOLTAGE (VDD) = 15V FREQUENCY OFFSET (fMIN) (Hz) 106 105 104
R2 = 10k
SUPPLY VOLTAGE (VDD) = 10V VCOIN = VSS INHIBIT = VSS
10V 5V 15V 10V 5V 15V 10V 5V 10
AMBIENT TEMPERATURE (TA) = -55oC +125oC R2 = 1M -55oC +125oC -55oC
103 102
R2 = 100k
VCO TIMING CAPACITOR (CI) (F) TYPICAL fMIN UNIT-TO-UNIT VARIATION VDD (V) 5 10 15 fMIN/fMIN (%) 25 20 25
+125oC 10 1 10-5 10-4 10-3 10-2 10-1 1 VCO TIMING CAPACITOR (CI) (F) 10
FIGURE 6. TYPICAL FREQUENCY OFFSET AS A FUNCTION OF C1 AND R2 FOR VDD = 5V, 10V, AND 15V
FIGURE 7. FREQUENCY OFFSET AS A FUNCTION OF C1 AND R2 FOR AMBIENT TEMPERATURES OF -55oC to 125oC
8 6 4 2
AMBIENT TEMPERATURE (TA) = +25oC fMAX WHEN VCOIN = VDD INHIBIT = VSS fMIN WHEN VCOIN = VSS AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VDD/2, R2 = INHIBIT = VSS CL = 50pF 105 SUPPLY VOLTAGE (VDD) = 15V 104 10V 103 5V 102 CL = 50pF 1F 50pF 1F
100 fMAX/fMIN SUPPLY VOLTAGE (VDD) = 5V, 10V 15V VCO POWER DISSIPATION (PD) (W)
8 6 4 2
10
8 6 4 2
1
2 4 68 2 4 68 2 4 68 2 4 68
0.01
0.1
1 R2/R1
10
100
50pF 1F
TYPICAL fMAX/fMIN UNIT-TO-UNIT VARIATION VDD (V) 5 10 15 fMAX/fMIN (%) 12 8 12 10
2 46 8 2 46 8 2 46 8
10
102 R1 (k)
103
104
FIGURE 8. TYPICAL fMAX/fMIN AS A FUNCTION OF R2/R1
FIGURE 9. TYPICAL VCO POWER DISSIPATION AT CENTER FREQUENCY AS A FUNCTION OF R1
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894
CD4046BMS Typical Performance Characteristics
VCO POWER DISSIPATION (PD) (W) AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VSS CL = 50pF 105 SUPPLY VOLTAGE (VDD) = 15V
(Continued)
VCO POWER DISSIPATION (PD) (W)
AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VDD/2, R1 = R2 = 104 SUPPLY VOLTAGE (VDD) = 15V 103 10V 102
104 10V 103 5V 102
CL = 50pF 1F 50pF 1F 50pF 1F
5V
101
10
2 46 8 2 46 8 2 46 8
1
2 46 8 2 46 8 2 46 8
10
102 R2 (k)
103
104
10
102 Rs (k)
103
104
FIGURE 10. TYPICAL VCO POWER DISSIPATION AT fMIN AS A FUNCTION OF R2
AC-COUPLED SIGNAL INPUT VOLTAGE (mV) (PEAK-TO-PEAK, SINE WAVE) VDD SUPPLY VOLTAGE (VDD) = 15V 2k
FIGURE 11. TYPICAL SOURCE FOLLOWER POWER DISSIPATION AS A FUNCTION OF RS
8 6 4 2
20k LINEARITY - PERCENT 13 VOUT
8 6 4 2
AMBIENT TEMPERATURE (TA) = +25oC VDD = 10V, VCOIN = 5V 1V, R2 =
104
8 6 4 2
2k 10V
10
8 6 4 2
103
8 6 4 2
VSS OUTPUT CIRCUIT
1
8 6 4 2
f0 =
102
8 6 4
5V
f(4V) + f(6V) 2 1 f0 - f(5V) f0
4 68 2
CL = 50pF 100pF 1000pF
0.1F
10
2 2 46
AMBIENT TEMPERATURE (TA) = +25oC PHASE COMPARATOR II
82 46 82
2
% LINEARITY =
2 4 68 2
x 100
4 68 2
0.01F
4 68
10-1
8
46
82
1
10 10 SIGNAL INPUT FREQUENCY (fIN) (kHz)
103
46
104
10-1
1
10 R1 (k)
102
103
FIGURE 12. AC-COUPLED SIGNAL INPUT VOLTAGE AS A FUNCTION OF SIGNAL INPUT FREQUENCY
FIGURE 13. TYPICAL VCO LINEARITY AS A FUNCTION OF R1 AND C1 AT VDD = 10V
8 6 4 2
AMBIENT TEMPERATURE (TA) = +25oC VDD = 10V, VCOIN = 5V 1V, R2 =
LINEARITY - PERCENT
10
8 6 4 2
CL = 50pF f(6V) + f(9V) 2 f0 - f(7.5V) f0
4 68 2
100pF
0.1F
1
8 6 4 2
f0 =
% LINEARITY =
2 4 68 2
x 100
4 68 2
10-1 10-1 1
1000pF 0.01F 0.1F
4 68
10 R1 (k)
102
103
FIGURE 14. TYPICAL VCO LINEARITY AS A FUNCTION OF R1 AND C1 AT VDD = 15V
7-895
CD4046BMS
I SIGNAL INPUT (TERM 14) VCO OUTPUT (TERM 4) = COMPARATOR INPUT (TERM 3) PHASE COMPARATOR II OUTPUT (TERM 13) VCO INPUT (TERM 9) = LOW-PASS FILTER OUTPUT PHASE PULSE (TERM 1) NOTE: DASHED LINE IS AN OPEN CIRCUIT CONDITION (3RD STATE)
II
III VDD
-VDD -VSS -VDD -VSS -VDD -VSS
PHASE 13 COMPARATOR II OUTPUT
20K
2K
2K
VSS
FIGURE 15. TYPICAL WAVEFORMS FOR COS/MOS PHASE-LOCKED LOOP EMPLOYING PHASE COMPARATOR II IN LOCKED CONDICTION
FIGURE 16. PHASE COMPARATOR II OUTPUT LOADING CIRCUIT
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-896

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